Individual memory chips used for random access memory (RAM) in digital systems are commonly mounted on modules such as a single in-line memory module (SIMM) or a dual in-line memory module (DIMM). Each memory module includes several individual memory chips mounted on a single module substrate such as a printed circuit board, for example. The memory modules are mounted on a system substrate or motherboard. Digital signals are driven to the memory chips from a driver which is commonly located on a separate chip mounted on the system motherboard. A network or net of conductors, commonly referred to as transmission lines or signal lines, carry each signal from the driver to the memory module and ultimately to the memory chips. Since many different signals are commonly transferred to the memory module, there are usually many parallel sets of signal lines, each extending from a driver to the memory chips. Traditionally, the impedance of all signal lines in a system board has a single value, 50 or 60 ohns for example.
A memory chip on a memory module represents a capacitive load on the signal line to which the memory chip is coupled. Each of these capacitive loads will cause a reflection of the signal applied to the signal line. In the case of a memory module with multiple memory chips coupled to a module signal line, the effect of the multiple capacitive loads is related to the spacing between the loads. If the magnitude of the signal time of flight between two loads is comparable to the rise time of the signal, the reflection will cause significant rise time degradation. The time of flight refers to the time it takes a signal to travel between two points, while the rise time refers to the time it takes for a digital signal to go from a low level voltage to a high level voltage. For example, in a single in-line memory module the time of flight between memory chips may be about 200 to 300,picoseconds. This time of flight is comparable to the driver rise time of about 500 to 1000 picoseconds. In this example, a signal propagating on the signal line to which the memory chips are coupled will experience a significant rise time degradation from all memory chips. This signal rise time degradation may interfere with the desired signals driven on the signal line and thus the operation of the system.
The time of flight of signals between the memory chips of a module may be reduced by reducing the spacing between the chips. One way to reduce the spacing is to mount the chips perpendicularly to the module substrate. U.S. Pat. No. 5,397,747 shows a chip packaging arrangement which includes perpendicularly mounted memory chips. However, even if the memory chip spacing is reduced to reduce the rise time degradation caused by the reflection produced at the memory chips themselves, the multiple capacitive loads on the chip signal line also reduce the effective impedance exhibited by the signal line. This reduced effective impedance in the chip signal line creates an impedance mismatch at the boundaries in the net between regions with and without memory chip couplings, and this mismatch produces a signal reflection.